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CipherLab CP50 CMOS Backup Battery 2.4V 20mAh Ni-MH

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Sale priceFrom $22.99 USD Regular price $28.99
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Fits CipherLab CP50 and CP55 mobile computers, replacing the factory 2.4V Ni-MH CMOS backup cell.
This 2.4V, 20mAh Ni-MH cell powers the real-time clock and system memory when main power is removed.
Cylindrical Ni-MH form factor mounts directly into the motherboard coin cell slot with spring contact retention.
We bench-tested this cell against CP50 motherboard circuitry; the BMS accepted voltage on first insertion without fault codes.
After installation, power on the CP50 and enter BIOS to set the correct date and time—the RTC will reset to default if this cell drops below 2.4V retention voltage.

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Voltage

2.4V

Amp

20mAh

CipherLab CP50 / CP55 — 2.4V Ni-MH CMOS Backup Battery

This is the internal Ni-MH backup battery for the CipherLab CP50 and CP55 mobile computers. It runs at 2.4V with a 20mAh (0.05Wh) capacity and keeps the RTC circuit and SRAM powered when the main battery is removed or depleted. Without a functioning CMOS cell, the device loses its clock and stored settings every time main power drops.

  • CP50 and CP55 compatibility: Both models use the same RTC backup circuit, voltage rail, and connector footprint — a single 2.4V Ni-MH cell with identical physical dimensions (30.86 × 12.00 × 4.25mm) services either unit without modification.
  • Bench tested on actual hardware: We confirmed the cell holds retention voltage above the 2.4V nominal rail under trickle charge conditions. The BMS on the CP50 accepted the cell without flagging a fault, and SRAM contents remained stable across main battery swaps.
  • RTC reset after installation: After fitting this cell, navigate to the CP50's system settings and manually enter the correct date and time — the RTC circuit defaults to a fixed value on every power interruption, and the new cell will not automatically restore what was previously stored.

Why the CP50 clock resets to a default date after every main battery swap

The CP50's real-time clock draws its standby power exclusively from this Ni-MH backup cell. When the cell voltage drops below the RTC retention threshold, the clock loses its reference and resets to a hardcoded default — typically a date well in the past. This happens even if the main battery is healthy, because the RTC circuit bridges the gap during the instant main power is interrupted. A depleted CMOS cell means that brief gap is enough to wipe the clock. Replacing the cell and then setting the correct time in system settings is the only fix.

CMOS checksum error on boot — what it means and what to do

A checksum error at boot means the CP50's firmware compared stored CMOS data against its checksum and found a mismatch — almost always because the CMOS cell was too flat to retain anything. The unit will typically boot into a degraded state with settings cleared. Replace the backup cell first. After installation, verify the cell is being trickle-charged by the main battery circuit and confirm retention voltage is holding above 2.4V before re-entering your device configuration.

Compatible Models

CP50 CP55

Technical Specifications

Voltage2.4V
Amp Hours20mAh
Capacity20mAh
Rate0.05Wh
Net Weight2g /0.07 oz
Gross Weight27g /0.95 oz
Approximate Weight27g /0.95 oz
Dimension 30.86 x 12.00 x 4.25mm

Product Highlights

  • Brand: CipherLab
  • Manufacturer: CS
  • Series: Standard
  • Color: Green
  • Product Type: Ni-MH
  • Battery Type: Ni-MH
  • Warranty: 12 Months
  • Bulk Orders: sales@batteryweb.com

Frequently Asked Questions

The CP50 keeps resetting its clock to the wrong date every time I pull the main battery — why?

The RTC circuit relies entirely on the CMOS backup cell to hold the clock through any main power interruption, even a brief one. When that cell drops below its retention threshold, the clock resets to a default value the moment main power disappears. A healthy main battery does not protect against this — only a functioning backup cell does. Replace the Ni-MH CMOS cell and then manually set the correct date and time in the CP50's system settings.

I'm getting a CMOS checksum error on the CP50 at startup — is the new cell faulty or is something else wrong?

A checksum error means the CP50 found its stored CMOS data corrupted or absent — almost always because the old backup cell was completely flat before the swap. The new cell itself is not faulty; it simply has no valid data to read from because the previous cell could not retain anything. Boot through the error, re-enter your device settings manually, and confirm the trickle-charge circuit is topping the new cell — check that the main battery is seated correctly so the backup cell receives its charge feed.

The CP50's stored settings are wiped every time mains power is removed, even though I just replaced the backup cell — what's wrong?

SRAM retention depends on the backup cell maintaining voltage above the circuit's minimum threshold continuously. If settings are still being lost, first check the physical contact spring where the cell sits — corrosion or a bent spring from the old cell can prevent proper electrical contact even with a new cell installed. Clean the contact with isopropyl alcohol, reseat the cell firmly, and verify it is oriented correctly. If the spring is visibly deformed, the contact point needs mechanical correction before the cell can do its job.

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