Intermec CN2 CMOS Replacement Battery 3.6V 20mAh Ni-MH

Intermec CN2 / CN2B / 6400 — 3.6V Ni-MH CMOS Backup Battery (317-200-001)

This is the internal CMOS backup battery for the Intermec CN2, CN2B, and 6400 mobile computers. It runs at 3.6V with a 20mAh capacity and holds the real-time clock and system configuration in SRAM when the main battery is removed or fully discharged. When this cell drops below the RTC retention threshold, the device loses its clock, stored settings, and operational parameters on every power cycle.

• CN2, CN2B, and 6400 compatibility: All three models share the same internal CMOS circuit layout and use OEM part 317-200-001. The connector, cell geometry (39.00 × 12.60 × 6.00mm), and voltage rail are identical across this family, so one cell covers all three platforms.
• Bench tested on actual hardware: We verified retention voltage holds above the 2.8V SRAM minimum under continuous low-draw load. The BMS circuit on these units does not trip — the CMOS cell feeds the RTC directly, and we confirmed stable clock retention through a full main battery swap cycle.
• Post-installation clock correction: After fitting this cell, navigate to the CN2's date and time settings and manually enter the correct values, then save. The CMOS cell powers the RTC circuit, and the clock resets to a factory default any time the cell is interrupted — including during the swap itself.

Clock resetting to a default date after every main battery swap on the CN2

The CN2 keeps its real-time clock alive through main battery changes using this 3.6V Ni-MH cell. When the cell drops below approximately 2.8V, it can no longer sustain the RTC circuit during the switchover window. The result is the clock falling back to a factory default — typically a date in 2000 or 2001 — every time the main pack is pulled. Replacing the CMOS cell and manually resetting the clock and date in the device settings corrects this immediately.

CMOS checksum error on boot after the CN2 sat unused for an extended period

A checksum error on boot means the CMOS cell has discharged far enough that SRAM content is no longer valid — the device detects corrupted or missing configuration data and flags it at startup. This is a different symptom from a simple wrong clock: the entire stored configuration, not just the RTC, has been lost. Fitting a fresh 317-200-001 cell restores SRAM power. After replacement, re-enter all device configuration settings from scratch, then verify the boot sequence completes without the checksum error before returning the unit to service.